The pin electronics card is a printed circuit board included in a test head portion of an LSI tester. On this printed circuit board, a driver circuit for supplying a signal directly to a DUT (device under test) and a comparator for receiving a signal directly from the DUT are formed.
Since a high throughput is required of the LSI tester, a driver circuit for pin electronics card is required to switch the output voltage at high speed. In the conventional driver circuit for pin electronics card, therefore, the output voltage at the output terminal is switched at high speed by using a diode bridge.
An example of a driver circuit using a diode bridge that can be used for a pin electronics card will now be described with reference to FIG. 3.
A driver circuit shown in FIG. 3 includes first and second diode bridges 1 and 2 in order to switch an output voltage at an output terminal 3 between a high level voltage (VH) and a low level voltage (VL).
The first diode bridge 1 includes four diodes D1 to D4. The diodes D1 and D2 are connected in series. The diodes D3 and D4 are also connected in series. And the diodes D1 and D2 and the diodes D3 and D4 are connected in parallel.
In addition, a first transistor Q1 is provided between a node N1a between the diodes D1 and D3 and a high voltage source 4. A second transistor Q2 is provided between a node N1b between the diodes D2 and D4 and a low voltage source 5. A node N1c between the diodes D3 and D4 is connected to the output terminal 3.
An analog buffer 6 having high input impedance and low output impedance is connected to the output terminal 3. By connecting the analog buffer 6, an abruptly changing voltage waveform can be output to an external circuit (such as a DUT) without being affected by the external circuit.
In addition, stray capacitance C is formed between the output terminal 3 and a common potential.
A node N1d is provided between the diode D1 and the diode D2. A transistor Q5 is connected between the node N1d and the high voltage source 4, and a transistor Q6 is connected between the node N1d and the low voltage source 5.
A second diode bridge 2 includes four diodes D5 to D8. The diodes D5 and D6 are connected in series. The diodes D7 and D8 are also connected in series. And the diodes D5 and D6 and the diodes D7 and D8 are connected in parallel.
In addition, a third transistor Q3 is provided between a node N2a between the diodes D5 and D7 and the high voltage source 4. A fourth transistor Q4 is provided between a node N2b between the diodes D6 and D8 and the low voltage source 5. A node N2c between the diodes D7 and D8 is connected to the output terminal 3.
A node N2d is provided between the diode D5 and the diode D6. A transistor Q7 is connected between the node N2d and the high voltage source 4, and a transistor Q8 is connected between the node N2d and the low voltage source 5.
If in such a circuit configuration the transistors Q1 and Q2 are in the on-state (conduction state between the source and node) and the transistors Q3 and Q4 are in the off-state (non-conduction state between the source and node), then an output voltage (Vout) becomes the high level voltage (VH). On the other hand, if the transistors Q1 and Q2 are in the off-state and the transistors Q3 and Q4 are in the on-state, then the output voltage (Vout) becomes the low level voltage (VL; VL<VH).
The on/off states of the transistors Q1 to Q4 are controlled respectively individually by control signals that are respectively applied from control signal sources *PH, PH, *PL and PL. Each of the control signals assumes a value of either the H level or the L level, and has a signal waveform of a pulse form.
Table 1 shows a logic table of the driver circuit.
TABLE 1InputTransistTransistTransistTransistOutputlogicor Q1or Q2or Q3or Q4potential*PH: LONONOFFOFFVH PH: H*PL: H PL: L*PH: HOFFOFFONONVL PH: L*PL: L PL: H
Operation of switching the output voltage at the output terminal from the low level to the high level will now be described.
First, when switching the output voltage (Vout) from the low level (VL) to the high level (VH), the transistors Q1 and Q2 are switched from the off-state to the on-state and the transistors Q3 and Q4 are switched from the on-state to the off-state.
As a result, a current from a constant current source I20 flows to the stray capacitance C through the transistor Q1, the node N1a, the diode D3, and the node N1c, as shown in FIG. 3. This current is referred to as first transition current I2b.
The value of the first transition current I2b is indicated by a charging current (ΔIcc) supplied to the stray capacitance C. The maximum current does not exceed the stationary current I20.
Since the value of the first transition current I2b flows to the stray capacitance C, the stray capacitance C is charged. As a result of this charging, the output voltage (Vout) at the output terminal 3 rises from the low level (VL) to the high level (VH), and it is switched.
If the first transition current I2b flows through the diode D3 in the first diode bridge 1, then no current flows through the diodes D1 and D4. In order to balance the first diode bridge 1, therefore, a first balance current I2a from the transistor Q5 flows through the diode D2.
In other words, since the charging current (ΔIcc)(the first transition current I2b) flows through the diode D3, the first balance current I2a flows through the diode D2, which is disposed in a position opposed to that of the diode D3 (i.e., which is not connected directly to the diode D3) in order to balance the first diode bridge 1.
Thereafter, the first balance current I2a flows from the diode D2 to the constant current source I20 via the transistor Q2.
The first balance current I2a exhibits a value equal to that of the first transition current I2b. Its maximum current does not exceed the stationary current I20.
When the stray capacitance C is charged. up to the voltage VH and the output voltage (Vout) at the output terminal 3 has reached the high level (VH) (i.e., when a shift from the transition state to the stationary state is conducted), supply of the first transition current I2b to the stray capacitance C is finished, and the stationary current I20 begins to flow instead of the first transition current I2b as shown in FIG. 4. The stationary current I20 flows from a constant current source I20 on the high voltage source 4 side to a constant current source I20 on the low voltage source 5 side via the transistor Q1, the first diode bridge 1 and the transistor Q2.
And since the flow of the first transition current I2b is finished, the flow of the first balance current I2a that has flown through the diode D2 is also finished.
In a stationary state obtained after the output voltage (Vout) at the output terminal has been switched from the low level (VL) to the high level (VH), the stationary current I20 flows from a constant current source I20 on the high voltage source 4 side to a constant current source I20 on the low voltage source 5 side via the transistor Q1, the first diode bridge 1 and the transistor Q2.
At the node N1a in the first diode bridge 1, the stationary current I20 is divided into a current that flows through the diode D1 and a current that flows through the diode D3. And the current that flows through the diode D1 and the diode D2 and the current that flows through the diode D3 and the diode D4 join at the node N1b, and a resultant current flows to the transistor Q2.
Operation of switching the output voltage at the output terminal from the high level to the low level will now be described.
When switching the output voltage (Vout) from the high level (VH) to the low level (VL), the transistors Q1 and Q2 are switched from the on-state to the off-state and the transistors Q3 and Q4 are switched from the off-state to the on-state.
As a result, a discharging current from the stray capacitance C flows to the constant current source I20 of the low voltage source 5 side via the node N2c, the diode D8, the node N2b and the transistor Q4 in the cited order as shown in FIG. 3. This discharging current is referred to as second transition current I2d.
The transistors Q1 and Q2 are turned off, and the transistors Q3 and Q4 are turned on. Since the discharging current (second transition current I2d) flows from the stray capacitance C to the low voltage source 5 side, the output voltage (Vout) at the output terminal 3 falls from the high level (VH) to the low level (VL) and it is switched.
If the second transition current I2d flows through the diode D8 in the second diode bridge 2, then a second balance current I2c from the transistor Q3 flows through the diode D5 in order to balance the second diode bridge 2.
In other words, since the discharging current flows through the diode D8, the second balance current I2c flows through the diode D5, which is disposed in a position opposed to that of the diode D8 (i.e., which is not connected directly to the diode D8), in order to balance the second diode bridge 2.
Thereafter, the second balance current I2c flows from the diode D5 to the low voltage source 5 via the transistor Q8. The second balance current I2c is equal in value to the second transition current I2d.
When discharging from the stray capacitance C is finished and the output voltage (Vout) at the output terminal 3 has reached the low level (VL) (i.e., when a shift from the transition state to the stationary state is conducted), flow of the second transition current I2d is finished.
Therefore, the second balance current I2c, which has flown through the diode D5, is also finished. Instead of the second balance current I2c, a stationary current I20 begins to flow through the transistor Q4 via the transistor Q3 and the second diode bridge 2 as shown in FIG. 4.
At the node N2a in the second diode bridge 2, the stationary current I20 is divided into a current that flows through the diode D5 and a current that flows through the diode D7. And the current that flows through the diode D5 and the diode D6 and the current that flows through the diode D7 and the diode D8 join at the node N2b, and a resultant current flows to the transistor Q4.
In a driver circuit for pin electronics card having such a configuration, the output voltage (Vout) is switched from the low level (VL) to the high level (VH), and the stationary current continues to flow even after the stationary state has been reached. In contrast, the output voltage (Vout) is switched from the high level (VH) to the low level (VL), and the stationary current continues to flow even after the stationary state has been reached.
Therefore, the driver circuit shown in FIG. 3 has a problem that power dissipation in the stationary state does not become small.
As a solution for this problem, it is considered to decrease the stationary current I20.
However, the slew rate (switching speed) conducted when switching the level of the output voltage is determined by the stray capacitance C and the charging current (ΔIcc). If the stationary current I20 is decreased in order to decrease the power dissipation, then, a problem arises in that the slew rate falls.
Thus in the driver circuit shown in FIG. 3, it is difficult to achieve both the reduction of the power dissipation and the maintenance of the high slew rate.
Especially, when the driver circuit is used for the pin electronics card, it has been a problem to output a voltage waveform that is steeper in the rising edge and the falling edge to the DUT. In other words, it has been demanded to provide a technique for making the slew rate of level switching in the output voltage at the output terminal of the driver circuit faster.